Volume 2-0724

July 2024
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This second volume of the Advanced Packaging Update includes an analysis of OSAT financials; chiplet packaging applications and market forecast; and HBM trends. A special section on RDL as an alternative to silicon interposer is included. Developments in build-up substrate are presented, along with an assessment of alternatives such as glass, silicon, and ceramic core substrates. TechSearch International’s annual survey on substrate design rules is presented, with special coverage of suppliers of laminate flip chip BGA and CSP substrates worldwide. The design rules include body size, core thickness, via and pad diameter, minimum bump pitch supported, and substrate finish.
  • Contents…
    • 1 Industry and Economic Trends
      • 1.1 Economic Outlook
        • 1.1.1 China's Economy
        • 1.1.2 U.S. Macroeconomic Trends
      • 1.2 Semiconductor Industry Trends
    • 2 OSAT Financial Analysis
      • 2.1 Market Overview
      • 2.2 OSAT Market Performance
      • 2.3 Company Highlights
        • 2.3.1 ASE Holdings
        • 2.3.2 Amkor Technology
        • 2.3.3 JCET Group
        • 2.3.4 Tongfu Microelectronics
        • 2.3.5 Powertech Technology
        • 2.3.6 UTAC
        • 2.3.7 Huatian
        • 2.3.8 KYEC
        • 2.3.9 ChipMOS
        • 2.3.10 Chipbond
      • 2.4 Outlook
    • 3 Packaging Chiplets
      • 3.1 Chiplet Packages
      • 3.2 Chiplet Architectures
        • 3.2.1 AMD
        • 3.2.2 Amazon
        • 3.2.3 Apple
        • 3.2.4 Broadcom
        • 3.2.5 Intel
        • 3.2.6 Marvell
        • 3.2.7 Nvidia
      • 3.3 Future Chiplet Applications
        • 3.3.1 Automotive
        • 3.3.2 Mobile
      • 3.4 Chiplet Package Market Forecast
      • 3.5 HBM Demand and Trends
        • 3.5.1 Supply and Demand
        • 3.5.2 HBM Process Challenges
        • 3.5.3 HBM and Package Assembly
        • 3.5.4 Hybrid Bonding for HBM
          • 3.5.4.1 Samsung
          • 3.5.4.2 SK Hynix
          • 3.5.4.3 Micron
    • 4 RDL Interposers
      • 4.1 TSMC
      • 4.2 Samsung
      • 4.3 OSATs
        • 4.3.1 Amkor Technology
        • 4.3.2 ASE
        • 4.3.3 AOI Electronics
        • 4.3.4 JCET
        • 4.3.5 SPIL
        • 4.3.6 Powertech Technology
      • 4.4 Substrate and Technology Suppliers
        • 4.4.1 Deca
        • 4.4.2 Dia Nippon Printing
        • 4.4.3 SiPlus
        • 4.4.4 Shinko Electric
        • 4.4.5 Unimicron
      • 4.5 Research Consortia
        • 4.5.1 IME
        • 4.5.2 Fraunhofer IZM
        • 4.5.3 Resonac JOINT2
    • 5 New Substrate Developments
      • 5.1 Large Body Build-up Substrates
      • 5.2 Silicon Core Substrates
      • 5.3 Ceramic Core Substrates
      • 5.4 Glass Core Substrates
        • 5.4.1 Absolics
        • 5.4.2 FICT
        • 5.4.3 Intel
        • 5.4.4 Dai Nippon Printing
        • 5.4.5 Qorvo
        • 5.4.6 Sony
        • 5.4.7 Toppan
        • 5.4.8 Unimicron
      • 5.5 Challenges
        • 5.5.1 Controlling Glass Cracking
          • 5.5.1.1 Singulation Methods
        • 5.5.2 Limitations to Number of Vias
        • 5.5.3 Reliability
        • 5.5.4 Alternative Core Materials
        • 5.5.5 Economic Considerations
    • ​6 Substrate Design Rules
      • 6.1 Today's Laminate Feature Size
      • 6.2 Company Design Rules
        • 6.2.1 ACCESS Semiconductor
        • 6.2.2 ASE Materials
        • 6.2.3 AT&S
        • 6.2.4 Daeduck
        • 6.2.5 Daisho Denshi
        • 6.2.6 FICT
        • 6.2.7 GS Swiss PCB
        • 6.2.8 Haesung DS
        • 6.2.9 Ibiden
        • 6.2.10 Kinsus Interconnect Technology
        • 6.2.11 Korea Circuit Company
        • 6.2.12 Kyocera International
        • 6.2.13 LG Innotek
        • 6.2.14 Meiko
        • 6.2.15 Nan Ya PCB
        • 6.2.16 R&D Altanova
        • 6.2.17 Samsung Electro-Mechanics
        • 6.2.18 Shennan Circuits
        • 6.2.19 Shinko Electric
        • 6.2.20 Simmtech
        • 6.2.21 Toppan
        • 6.2.22 TTM Technologies
        • 6.2.23 Unimicron
    • ​Appendix: Substrate Suppliers
    • References
  • Figures…
    • 1.1 Monthly U.S. housing starts.
    • 4.1 TCB profile for FOCoS bridge process.
    • 4.2 Resonac embedded die fabrication process.
    • 5.1 Ceramic core package.
  • Tables…
    • 2.1 Revised Ranking of Top 20 Publicly Traded OSATs
    • 2.2 New Top 20 OSATs Quarterly Revenue
    • 3.1 Packages for Chiplet Architectures
    • 3.2 Apple’s Mobile Processor Trends
    • 3.3 Qualcomm Mobile Processor Trends
    • 3.4 Google Tensor Mobile Processor Trends
    • 3.5 Chiplet Package Market Forecast
    • 3.6 HBM Demand Forecast
    • 4.1 HBM3 High-Speed Interconnect Design Comparison
    • 5.1 CHIPS R&D-Specified Technical Targets
    • 5.2 Silicon Core Substrate Design Rules and Properties
    • 5.3 Resonac Core Material Properties
    • 6.1 Selected Build-up FC-PBGA Substrate Suppliers
    • 6.2 Selected Build-up FC-CSP Substrate Suppliers
    • 6.3 Design Rules for ACCESS FC-BGA Substrates
    • 6.4 Design Rules for ACCESS Coreless Substrates
    • 6.5 Design Rules for ACCESS FC-CSP Substrates
    • 6.6 Design Rules for ACCESS Wire Bond CSP Substrates
    • 6.7 Design Rules for ASE PBGA/CSP Substrates
    • 6.8 Design Rules for AT&S FC-PBGA Substrates
    • 6.9 Design Rules for Daeduck FC-CSP/SiP Substrates
    • 6.10 Design Rules for Daeduck Thin WB Substrates
    • 6.11 Design Rules for Daeduck FC-PBGA Substrates
    • 6.12 Design Rules for Daisho Denshi PBGA/CSP Substrates
    • 6.13 Design Rules for FICT FC-PBGA Substrates
    • 6.14 Design Rules for Ibiden FC-PBGA Substrates
    • 6.15 Design Rules for Kinsus FC-PBGA Substrates
    • 6.16 Design Rules for Kinsus FC-CSP Substrates
    • 6.17 Design Rules for Kinsus PBGA/CSP Substrates
    • 6.18 Design Rules for Kinsus Coreless Substrates
    • 6.19 Design Rules for KCC FC-CSP Substrates
    • 6.20 Design Rules for KCC UT-CSP Substrates
    • 6.21 Design Rules for Kyocera FC-PBGA Substrates
    • 6.22 Design Rules for Kyocera FC-CSP Substrates
    • 6.23 Design Rules for LG Innotek CSP Substrates
    • 6.24 Design Rules for LG Innotek FC-CSP Substrates
    • 6.25 Design Rules for LGIT FC-PBGA Substrates
    • 6.26 Design Rules for Meiko FC-PBGA Substrates
    • 6.27 Design Rules for Meiko PCB PBGA Substrates
    • 6.28 Design Rules for Nan Ya PCB FC-PBGA Substrates
    • 6.29 Design Rules for Nan Ya PCB PBGA/CSP Substrates
    • 6.30 Design Rules for Nan Ya FC-CSP Substrates
    • 6.31 Design Rules for Nan Ya PCB FC-PBGA Coreless Substrates
    • 6.32 Design Rules for R&D Altanova FC-PBGA Substrates
    • 6.33 Design Rules for SEMCO FC-PBGA Substrates
    • 6.34 Design Rules for SEMCO PBGA/CSP Substrates
    • 6.35 Design Rules for SEMCO FC-CSP Substrates
    • 6.36 Design Rules for SCC PBGA/CSP Substrates
    • 6.37 Design Rules for Shinko Electric FC-BGA/LGA Substrates
    • 6.38 Design Rules for Shinko Electric FC-CSP Substrates
    • 6.39 Design Rules for Shinko Electric Coreless Substrates
    • 6.40 Design Rules for Simmtech PBGA/CSP Substrates
    • 6.41 Design Rules for Simmtech Coreless Substrates
    • 6.42 Design Rules for Toppan FC-PBGA Substrates
    • 6.43 Design Rules for CoreEZ® Substrates
    • 6.44 Design Rules for HyperBGA® Substrates
    • 6.45 Design Rules for TTM FC-PBGA Substrates
    • 6.46 Design Rules for Unimicron FC-PBGA Substrates
    • 6.47 Design Rules for Unimicron FC-CSP Substrates
    • 6.48 Design Rules for Unimicron PBGA/CSP Substrates
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  • Published July 2024
  • 116 pages
  • 4 figures / 60 tables
  • 98 PowerPoint slides
  • $8,750 corporate license (4 issues)
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