TechSearch International president Jan Vardaman served as co-author on a study from IPC that provides a thorough, data-driven analysis of the global semiconductor and advanced packaging ecosystem. The study, An Analysis of the North American Semiconductor and Advanced Packaging Ecosystem, highlights the role of advanced packaging in driving innovation in semiconductor designs.

The IPC report makes the case for congressional appropriations of more than $50 billion to support U.S. semiconductor manufacturing, while also underscoring the need to expand advanced packaging capabilities to support the increased production of chips. At a time when the semiconductor supply chain is facing immense pressure, increasing silicon production without bolstering domestic advanced packaging capabilities is likely to lengthen the semiconductor supply chain, as chips will still have to be sent abroad for packaging and assembly into finished products.

Access to the report is free to all.

TThe Worldwide Assembly & Test Facility Database provides a detailed global view of semiconductor back-end manufacturing facilities operated by integrated device manufacturers (IDMs) and outsourced semiconductor assembly and test (OSAT) companies.

The 2026 edition covers more than 820 facilities worldwide. It provides facility-level information on company ownership, location, operating status, assembly and packaging capabilities, test coverage, device focus, advanced packaging technologies, automotive certifications, substrate and interposer platforms, end-market focus, and selected site attributes.

The database helps users evaluate the global assembly and test footprint, compare regional capabilities, identify potential manufacturing partners, assess supply-chain exposure, and monitor the evolution of back-end capacity and technology.

What’s New in 2026

• Expanded global coverage to more than 820 facilities
• New and expanded fields covering silicon and compound semiconductor capability, compound semiconductor types, substrate/interposer platforms, end-market focus, and technology/module capability
• Updated facility operating status, ownership, location, assembly, test, device focus, and packaging capability information
• Updated Top 10 OSAT capital expenditure ranking and Top 20 OSAT revenue ranking

Features

• Company and Site Information: Company name, ownership, headquarters, plant site, address, region, website, and selected facility details
• Operating Profile: Facility status, plant type, assembly activity, test coverage, and operating history
• Assembly and Packaging Capabilities: Leadframe, laminate BGA/CSP, wafer-level packaging, bumping, TSV, modules, SiP, MCP, and advanced packaging technologies
• Device and Material Focus: Memory, logic/analog, power, RF, MEMS/sensors, CIS/opto/photonics, silicon usage, compound semiconductor capability, and compound semiconductor types including SiC, GaN, GaAs, and InP
• Market and Technology Attributes: Automotive certification; substrate/interposer platform, including laminate substrate, RDL, ceramic substrate, silicon interposer, and leadframe; end-market focus; technology/module capability; and notes
• OSAT Market Benchmarks: Top-company rankings by revenue and capital expenditures

Benefits & Applications

• Map global IDM and OSAT manufacturing footprints
• Assess regional concentration and supply-chain exposure
• Identify alternative assembly, packaging, and test partners
• Compare facility-level technology and device capabilities
• Support strategic planning, market analysis, sourcing, and competitive benchmarking
• Track facility openings, closures, expansions, and technology evolution

This 2024 edition of the Global Semiconductor Packaging Materials Outlook (GSPMO) is authored by TECHCET and TechSearch International, Inc., in cooperation with SEMI.

The report covers the packaging materials markets, including substrates, lead frames, bonding wire, encapsulation materials, underfill materials, die-attach, solder balls, wafer-level package dielectrics, and wafer-level plating chemicals. However, due to a lack of interest, this report did not include solder balls.

Global Semiconductor Packaging Materials Outlook is an essential business tool for anyone interested in the plastic packaging materials arena. Packaging materials directly affect semiconductors' performance, reliability, and cost, and advancements in packaging materials technology offer the potential for significant improvement across all these areas.

Features

• Technology trends
• Regional market size and forecast
• Five-year market forecast to 2028
• Market size by product segments in revenue and units
• Excel workbook file summarizing market information
• Supplier information and market share

Benefits

• Gain insights to worldwide packaging material technology trends, market size, and market forecast
• Learn about market drivers and advancements in packaging materials
• Use benchmark data to validate business opportunities and assumptions

Condensed Table of Contents

• Introduction
• Semiconductor Industry Market Status & Outlook
• Substrates
• Leadframes
• Bonding Wire
• Encapsulation Materials
• Underfill Materials
• Die Attach Materials
• Wafer Level Package Dielectrics
• Wafer Level Plating Chemicals
• Summary and Conclusion
• Appendices

Wafer level packaging (WLP) is often the most cost-effective approach for achieving miniaturization. However, using wafer level packaging for the wrong applications can be needlessly expensive. The significant differences between printed circuit board interconnect design rules and semiconductor interconnect design rules must be resolved by the package, and this presents unique challenges for wafer level packaging.

If miniaturization is not required, a wire bond package is usually the most cost-effective packaging approach. However, a modified wafer level packaging approach called fan-out wafer level packaging is one option that overcomes the traditional WLP I/O restrictions. In many cases, fan-out wafer level packaging or flip chip packaging is the lowest cost solution for applications requiring a moderate number of I/Os with some package size constraints.

This paper compares the total packaging cost of the following four technologies:

• Wire bond packaging
• Flip chip packaging
• Fan-in wafer level packaging
• Fan-out wafer level packaging

The analysis is accomplished using a comprehensive activity based cost model for each of the four package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), fabrication activities (redistribution layer creation, inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) are modeled and verified using multiple industry sources.

After successful collaboration on cost models for Wafer Level Packaging, Flip Chip, Wire Bond, and other technologies, SavanSys Solutions and TechSearch International released a cost trade-off model for 2.5D and 3D packaging technologies. While there are still technical barriers to high volume adoption of 2.5D and 3D packaging solutions, cost remains a primary obstacle. The question is not whether 2.5D and 3D stacks can be built, but rather which applications are appropriate for these technologies based on cost/performance.

The 2.5D & 3D Packaging Cost Model covers the total cost and yield from fabrication of the wafer to complete assembly, for both 2.5D and 3D applications. The user is able to edit a variety of parameters, including TSV and interposer characteristics, supplier specific inputs, and die preparation details. For parameters not known or specified, the model will estimate it based on other user entries and the latest industry knowledge. A detailed cost break down of the total process cost is generated for each analysis, allowing the user to pinpoint the exact steps in the process flow that contribute to cost. In addition, detailed manipulation of the process flow is available, allowing the user to disable or enter specific values for process steps.

• SavanSys develops the model software
• TechSearch helps with model calibration

Wafer level packaging (WLP) is often the most cost-effective approach for achieving miniaturization. However, using wafer level packaging for the wrong applications can be needlessly expensive. The significant differences between printed circuit board interconnect design rules and semiconductor interconnect design rules must be resolved by the package, and this presents unique challenges for wafer level packaging.

If miniaturization is not required, a wire bond package is usually the most cost-effective packaging approach. However, a modified wafer level packaging approach called fan-out wafer level packaging is one option that overcomes the traditional WLP I/O restriction. In many cases, fan-out wafer level packaging or flip chip packaging is the lowest cost solution for applications requiring a moderate number of I/Os with some package size constraints.

This paper compares the total packaging cost of the following four technologies:

• Fan-in wafer level packaging
• Fan-out wafer level packaging

• Flip chip packaging

• Wire bond packaging

The analysis is accomplished using a comprehensive activity based cost model for each of the four package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), fabrication activities (redistribution layer creation, inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) are modeled and verified using multiple industry sources.

• SavanSys develops the model software
• TechSearch helps with model calibration

In addition to performing our own teardowns of leading-edge system products, TechSearch International also markets teardown reports from Total Process Solution Study Group (TPSS) in Japan.