TechSearch International president Jan Vardaman served as co-author on a study from IPC that provides a thorough, data-driven analysis of the global semiconductor and advanced packaging ecosystem. The study, An Analysis of the North American Semiconductor and Advanced Packaging Ecosystem, highlights the role of advanced packaging in driving innovation in semiconductor designs.

The IPC report makes the case for congressional appropriations of more than $50 billion to support U.S. semiconductor manufacturing, while also underscoring the need to expand advanced packaging capabilities to support the increased production of chips. At a time when the semiconductor supply chain is facing immense pressure, increasing silicon production without bolstering domestic advanced packaging capabilities is likely to lengthen the semiconductor supply chain, as chips will still have to be sent abroad for packaging and assembly into finished products.

Access to the report is free to all.

The Worldwide Assembly & Test Facility Database is a comprehensive data file tracking over comprehensive report tracking over 500 total back-end facilities of IDMs and outsourced semiconductor assembly and testing manufacturers in China, Taiwan, Korea, Japan, Southeast Asia, Europe, and the Americas. This report is an essential business tool for anyone interested to learn more about the semiconductor back-end supply chain.

Details include:

• Plant site technology capability: Tape and Reel, Test
• Packaging assembly service offered: BGA, specific leadframe type such as QFP, QFN, SO, flip chip bumping, WLP, Modules/SIP, etc.
• Plant site specification: TSV, RF, Cu Pillar, RDL, etc.

Key Highlights

• 2022 edition includes over 30 new facility additions compared to the 2021 report
• The world's Top 20 OSAT companies in 2020 and 2021
• More than 200 companies and more than 500 total back-end facilities
• Over 325 facilities with Test capabilities
• Over 100 facilities offering leadframe CSP
• Over 80 bumping facilities, including over 50 with 300mm wafer bumping capacity
• More than 90 facilities offering WLCSP technology
• New facilities offering Fan-out wafer-level packaging (FOWLP) and Fan-out panel-level packaging (FOPLP)
• Over 110 OSAT facilities in China, over 100 in Taiwan, over 45 in Americas
• Over 50 IDM A&T facilities in Southeast Asia, around 25 in China, and nearly 20 in Americas

Features

• Manufacturing site information
• Packaging technology capabilities
• Plant site applications capabilities
• Type of services offered
• Manufacturing specialization by facility

Benefits

• Gain insight to worldwide IDM assembly/test and OSAT facilities capabilities and expertise
• Understand key packaging capabilities and technologies by IDM and OSAT
• A tool to identify new business opportunities and assess competition
• Empower your market research with verified, validated, and credible information

TECHCET and TechSearch International, in cooperation with SEMI, authored the 10th edition of the Global Semiconductor Packaging Materials Outlook, a comprehensive market research study that examines semiconductor packaging technology trends and their impact on the packaging materials markets. The report quantifies the packaging materials markets by segment and by region, highlights new opportunities for emerging package form factors, defines supplier market share, and presents market forecasts through 2027.

Global Semiconductor Packaging Materials Outlook is
an essential business tool for anyone interested in the plastic packaging materials arena. Packaging materials directly affect the performance, reliability and cost of semiconductors, and advancements in packaging materials technology offer the potential for significant improvement across all these areas.

Features

• Technology trends
• Regional market size
• Five-year market forecast
• Supplier market share
• Market size in revenue and units
• Capacity and utilization trends
• Supply chain issues

Benefits

• Gain insights to worldwide packaging material technology trends, market size, and market forecast
• Understand key package offerings and technologies
• Use benchmark data to validate business opportunities and assumptions

Condensed Table of Contents

• Introduction
• Semiconductor Packaging
• Substrates
• Leadframes
• Bonding Wire
• Mold Compounds
• Liquid Encapsulates
• Die Attach Materials
• Solder Balls
• Wafer Level Package
• Plating Chemicals
• Summary and Conclusion
• Appendices

Wafer level packaging (WLP) is often the most cost-effective approach for achieving miniaturization. However, using wafer level packaging for the wrong applications can be needlessly expensive. The significant differences between printed circuit board interconnect design rules and semiconductor interconnect design rules must be resolved by the package, and this presents unique challenges for wafer level packaging.

If miniaturization is not required, a wire bond package is usually the most cost-effective packaging approach. However, a modified wafer level packaging approach called fan-out wafer level packaging is one option that overcomes the traditional WLP I/O restrictions. In many cases, fan-out wafer level packaging or flip chip packaging is the lowest cost solution for applications requiring a moderate number of I/Os with some package size constraints.

This paper compares the total packaging cost of the following four technologies:

• Wire bond packaging
• Flip chip packaging
• Fan-in wafer level packaging
• Fan-out wafer level packaging

The analysis is accomplished using a comprehensive activity based cost model for each of the four package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), fabrication activities (redistribution layer creation, inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) are modeled and verified using multiple industry sources.

After successful collaboration on cost models for Wafer Level Packaging, Flip Chip, Wire Bond, and other technologies, SavanSys Solutions and TechSearch International released a cost trade-off model for 2.5D and 3D packaging technologies. While there are still technical barriers to high volume adoption of 2.5D and 3D packaging solutions, cost remains a primary obstacle. The question is not whether 2.5D and 3D stacks can be built, but rather which applications are appropriate for these technologies based on cost/performance.

The 2.5D & 3D Packaging Cost Model covers the total cost and yield from fabrication of the wafer to complete assembly, for both 2.5D and 3D applications. The user is able to edit a variety of parameters, including TSV and interposer characteristics, supplier specific inputs, and die preparation details. For parameters not known or specified, the model will estimate it based on other user entries and the latest industry knowledge. A detailed cost break down of the total process cost is generated for each analysis, allowing the user to pinpoint the exact steps in the process flow that contribute to cost. In addition, detailed manipulation of the process flow is available, allowing the user to disable or enter specific values for process steps.

• SavanSys develops the model software
• TechSearch helps with model calibration

Wafer level packaging (WLP) is often the most cost-effective approach for achieving miniaturization. However, using wafer level packaging for the wrong applications can be needlessly expensive. The significant differences between printed circuit board interconnect design rules and semiconductor interconnect design rules must be resolved by the package, and this presents unique challenges for wafer level packaging.

If miniaturization is not required, a wire bond package is usually the most cost-effective packaging approach. However, a modified wafer level packaging approach called fan-out wafer level packaging is one option that overcomes the traditional WLP I/O restriction. In many cases, fan-out wafer level packaging or flip chip packaging is the lowest cost solution for applications requiring a moderate number of I/Os with some package size constraints.

This paper compares the total packaging cost of the following four technologies:

• Fan-in wafer level packaging
• Fan-out wafer level packaging

• Flip chip packaging

• Wire bond packaging

The analysis is accomplished using a comprehensive activity based cost model for each of the four package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), fabrication activities (redistribution layer creation, inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) are modeled and verified using multiple industry sources.

• SavanSys develops the model software
• TechSearch helps with model calibration

In addition to performing our own teardowns of leading-edge system products, TechSearch International also markets teardown reports from Total Process Solution Study Group (TPSS) in Japan.