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System-in-Package: The New Wave in 3D Packaging

Technology advances and market drivers have produced a renaissance in multichip packaging solutions. System-in-Package (SiP) solutions are increasingly found in a broad range of market segments, including consumer electronics such as digital cameras and camcorders, automotive, military/aerospace, medical, computer, and telecommunications products. Each market segment has particular needs and drivers that require a diverse set of structures and configurations. SiP examples are provided, including details on the number and type of die, package type and body size, configuration, lead count, and substrate. Drivers for the use of SiP in each application area are described, along with performance requirements and functions.

The report answers the key question of how SiPs are different from multichip packages of the past. One application–wireless products–stands out as a high-volume driver that did not exist a dozen years ago when many multichip packages were first introduced. SiPs deliver increased functionality and performance in small form factor for mobile communication, resulting in significantly greater adoption rates than any previous multichip module. A variety of SiPs are found in the RF, digital baseband, and transceiver sections of mobile phone. Emerging applications for mobile phones include mini hard disks and camera modules. Both planar and stacked configurations are in use and several companies, including Philips, STMicroelectronics, and SyChip, have introduced integrated passive substrate solutions.

A five-year industry outlook and projections by market are provided for each application. With a unit growth rate of almost 20 percent CAGR between 2004 and 2009, semiconductor designers and fabs, along with substrate providers, assembly houses, circuit board manufacturers, EMS companies, and systems houses are experiencing the benefits of SiP and the changes brought about by its use. Each facet of the SiP supply chain, including design, procurement, manufacturing, assembly, and test, is analyzed. New concerns, including logistical and engineering issues, wafer thinning, and assembly, are addressed. The report explains how the issue of KGD has driven the development of new package configurations such as package-on-package and package-in-package. An insight into the relationship between SiP and system-on-chip (SoC) as both competing and complementary solutions is also included.

	System-in-Package: The New Wave in 3D Packaging
File size: 147.6 kb		Published: September 2005

Table of Contents
	Executive Summary
1	Introduction
1.1	History of Multichip Packaging
1.1.1	The First Wave–MCMs
1.1.1.1	A Definition for MCM
1.1.2	The Second Wave–MCPs
1.1.2.1	A Definition for MCP
1.1.3	Benefits of Multiple Chip Packaging
1.1.4	IC Integration–The SoC Movement
1.1.5	The New Wave–SiPs
1.1.5.1	Single Chip Packaging
1.1.5.2	Stacked Die Package
1.1.5.3	SiP Definition
1.1.5.4	SiP Packaging Alternatives
1.1.5.4.1	Planar
1.1.5.4.2	3D or Stacked Constructions
1.1.5.4.3	Technological Issues
1.1.5.5	SoC versus SiP
2	Markets and Applications
2.1	Mobile Phones and Wireless Products
2.1.1	Stacked Die Packages
2.1.1.1	Amkor Technology, Inc.
2.1.1.2	Advanced Semiconductor Engineering Group
2.1.1.3	Fujitsu Microelectronics
2.1.1.4	Siliconware Precision Industries Co., Ltd.
2.1.1.5	STATSChipPAC, Ltd.
2.1.2	Digital Baseband Modules
2.1.2.1	Intel
2.1.2.2	Texas Instruments
2.1.2.3	Freescale Semiconductor
2.1.3	Power Amplifier and RF Modules
2.1.3.1	Skyworks
2.1.3.2	SyChip
2.1.3.3	Agere
2.1.3.4	Amkor
2.1.3.5	Carsem
2.1.3.6	Cambridge Silicon Radio
2.1.3.7	Philips
2.1.3.8	RF Micro Devices
2.1.3.9	STMicroelectronics
2.1.3.10	Kyocera
2.1.4	Global Positioning Systems
2.1.5	Camera Modules
2.1.6	Mini Hard Disk
2.1.7	Future Packages
2.1.8	Wireless SiP Market Projections
2.2	Consumer Products
2.2.1	Sony
2.2.2	Renesas Technology
2.3	MP3 and DVD Players
2.4	Home Appliances
2.4.1	Consumer Product SiP Market Projections
2.5	Medical Electronics
2.5.1	Ultrasonic Diagnostic System
2.5.2	Capsule Endoscopy
2.5.3	Hearing Aids
2.5.4	Implantable Products
2.5.5	Future Applications
2.5.5.1	Implantables
2.5.5.2	Neuromuscular Stimulation
2.5.5.3	Artificial Vision
2.5.5.4	Disc Replacement
2.5.6	Medical SiP Market Projections
2.6	Computing Hardware
2.6.1	Personal Computing
2.6.2	Supercomputers/Mainframes/Servers
2.6.2.1	IBM
2.6.2.2	Hitachi
2.6.2.3	Fujitsu
2.6.3	FPGA Modules
2.6.4	Graphics Modules
2.7	High Performance Networking Hardware
2.7.1	Cisco
2.7.2	Zarlink
2.7.3	Optical Modules
2.7.4	Computer and Communication SiP Market Projections
2.8	Automotive Electronics
2.8.1	Automotive SiPs
2.8.1.1	Micronas
2.8.1.2	Delphi
2.8.1.3	Siemens/VDO
2.8.1.4	Freescale Semiconductor
2.8.1.5	Tire Pressure Sensors
2.8.2	Automotive SiP Market Projections
2.9	Defense and Aerospace Electronics
2.9.1	Aeroflex
2.9.2	Boeing
2.9.3	Endicott Interconnect
2.9.4	Interconnect Systems, Inc.
2.9.5	3D-Plus
2.9.6	Tessera
2.9.7	White Electronic Designs Corporation
2.9.8	Military/Aerospace SiP Market
3	Design
3.1	Issues and Challenges in Design
3.1.1	2D versus 3D Layout
3.1.2	Modeling and Simulation
3.1.2.1	Thermal Management
3.1.2.2	Mechanical Structure
3.1.2.3	Electrical Performance
3.1.2.4	Additional Technology Issues
3.1.3	Cost Modeling
3.1.4	It's a System
3.2	State of the Industry
3.2.1	Design Strategies
3.2.2	The Gap in Design, Modeling, and Simulation Tools
3.2.3	ITRS
4	Interconnect and Assembly
4.1	Assembly Issues and Trends
4.1.1	Die Thinning
4.1.2	Die Attach
4.1.3	Interconnect Methods
4.1.3.1	Wire Bond
4.1.3.2	Flip Chip
4.1.4	Substrates
4.1.4.1	New Substrates
4.2	Thermal Issues
4.3	Future Requirements
4.4	Impact of Environmental Requirements
5	Test
5.1	Single-Chip Module Process
5.2	Packaging of Multiple Devices
5.2.1	Known Good Die
5.2.1.1	Die Level KGD Technology
5.2.1.2	Wafer Level KGD
5.2.1.3	Statistical Test Methods and Reliability Screens
5.2.1.4	BIST
5.2.1.5	Issues with KGD
5.2.1.6	KGD Strategies for SiP
5.2.2	Substrate Test
5.2.3	Module Test
5.2.4	Design for Test and Test Strategies
5.3	Warranty
6	Contract Manufacturing
6.1	Unique Challenges of SiP Production
6.1.1	Component Traceability
6.1.2	Rework
6.2	Strengths of SATS and EMS Providers
7	Future Technology
7.1	Industry Roadmap for SiP
7.1.1	iNEMI
7.1.2	ITRS
7.1.3	SiP Consortium
7.2	3D Integration Wafer-to-Wafer Bonding
7.2.1	Through-hole Vias
7.2.2	Wafer-to-Wafer Bonding
7.3	System-on-Package
7.3.1	Digital SoP
7.3.2	RF SOP
7.3.3	Opto SOP
7.4	Ambient Intelligence

List of Figures
1	Reasons for adopting SiP.
2	Compartmentalization of SiP and SoC by memory capacity.
3	SiP market projections (millions of units).
1.1.	Mounting area reduction in BGA packaging.
1.2.	Position of SiP.
1.3.	Sharp's development history and roadmap.
1.4.	Package constructions for SiP.
1.5.	Intel's four die memory stack.
1.6.	Stacked memory die configuration with spacer.
1.7.	Package-on-package.
1.8.	Package-in-package.
1.9.	Effect of adding silicon to the stacked die package.
1.10.	SiP engine package comparison.
2.1.	Reasons for adopting SiP.
2.2.	Sony's 506iC mobile phone with stacked die.
2.3.	Intel SiP in palmOne PDA.
2.4.	Amkor's stacked die and stacked package products.
2.5.	ASE's SiP families.
2.6.	Intel's FSCSP.
2.7.	Intel's SiP in Motorola's E680 Tri-band mobile phone.
2.8.	TI SiP.
2.9.	SiP for digital baseband.
2.10.	Single package radio from Skyworks.
2.11.	Skyworks transceiver front end module (FEM).
2.12.	SyChip's SiP.
2.13.	Thin-film-on-silicon substrate with IPDs.
2.14.	SyChip's embedded module.
2.15.	Agere's WL1141 PHY RF SiP module.
2.16.	Philips sbSiP.
2.17.	Philips GPS receiver.
2.18.	PA module.
2.19.	Transceiver module.
2.20.	Transceiver RF ASIC on IPAD.
2.21.	Transceiver plus filters plus IPAD.
2.22.	Cross section of Motorola Instant GPS.
2.23.	Sharp's camera modules.
2.24.	Representative camera SiP from Fujitsu.
2.25.	Kyocera's SiP substrate for mobile phones.
2.26.	Kyocera's SiP substrate for a one-inch HDD.
2.27.	Wafer level SiP.
2.28.	Embedded wafer level package (EWLP).
2.29.	CPU EWLP module.
2.30.	EWLP SiP PoP.
2.31.	Digital camcorder with SiP.
2.32.	Evolution of SiP packaging in Sony's Cyber-Shot DSC.
2.33.	SiPs for camera modules.
2.34.	SiP for MP3 player.
2.35.	Cross sectional view of PillCam!"
2.36.	Bion neuromuscular stimulator.
2.37.	Theken disc replacement device.
2.38.	Itanium module without heat cap.
2.39.	Floor plan of the IBM z-990 module.
2.40.	The IBM z-990 module.
2.41.	POWER5 system architecture.
2.42.	The IBM POWER5 DCM.
2.43.	The IBM POWER5 module.
2.44.	IBM Blade and System Board.
2.45.	Hitachi module.
2.46.	Hitachi module with heat fins.
2.47.	Hitachi system board with SiP modules.
2.48.	Fujitsu's MCM before heatsink assembly.
2.49.	Fujitsu's MCM structure.
2.50.	Stacked FPGAs for server market.
2.51.	Graphics processor module.
2.52.	Cisco's network product evolution.
2.53.	Cisco base board assembly with daughter module.
2.54.	16-layer board.
2.55.	10-layer SiP.
2.56.	Network timing module.
2.57.	Cross section of Zarlink timing module.
2.58.	Micronas automotive package.
2.59.	Powertrain controller (top and bottom).
2.60.	Under-hood gearbox control.
2.61.	Tire pressure sensor.
2.62.	ACT527SC SiP.
2.63.	SiP for military application.
2.64.	SiP solution on organic substrate for military and avionics.
2.65.	SiP for NASA with FPGA and memory.
2.66.	RF 3D integration example.
2.67.	High density, four-die digital module.
2.68.	F-16 module.
3.1.	Traditional packaging layout and X-ray.
3.2.	Stacked die layout and X-ray in 3D environment.
3.3.	Trade-offs in stacked die versus stacked package designs.
3.4.	LSI combination of SiP at digital imaging products.
3.5.	SiP layout.
3.6.	Understanding and enabling the co-design environment.
5.1.	Single-chip module process flow.
5.2.	Reliability "bathtub" curve.
5.3.	Number of die and probability that they are good affect yield.
5.4.	KGD carrier process.
5.5.	Wafer level KGD process flow.
7.1.	Effect of adding die to the stack in the package.
7.2.	SiP Consortium technology roadmap.
7.3.	PRC's law for the systems of the next $1T industry.
7.4.	Research focus at PRC to realize SoP.
7.5.	Embedded decoupling with different technologies.
7.6.	Examples of component integration.
7.7.	Examples of optical component integration.
7.8.	Roadmap for Ambient Intelligence hardware technology platforms.

List of Tables
1	SiP Constructions
1.1	Comparison of Package Shape and Characteristics
1.2	SoC and SiP Strengths and Weaknesses
2.1	SiP Constructions for Mobile Phones
2.2	Stacked Die Package Constructions in Production
2.3	Stacked Die Trends at Amkor by Device Type
2.4	Stacked Die Trends at Amkor by Number of Die
2.5	Stacked Die Trends at ASE by Device Type
2.6	Stacked Die Trends at ASE by Number of Die
2.7	Stacked Die Trends at Fujitsu by Device Type
2.8	Stacked Die Trends at Fujitsu by Number of Die
2.9	Stacked Die Trends at SPIL by Device Type
2.10	Stacked Die Trends at SPIL by Number of Die
2.11	Stacked Die Trends at STATSChipPAC by Device Type
2.12	Stacked Die Trends at STATSChipPAC by Number of Die
2.13	Features of Kyocera's Mobile Phone SiP Substrate
2.14	SiP for Wireless Applications (millions of units)
2.15	SiP Constructions in Consumer Products
2.16	Comparison of a Stacked Die and a PoP
2.17	SiP for Consumer Applications (millions of units)
2.18	SiP for Medical Applications (thousands of units)
2.19	Itanium 2 Based High End Servers/Mainframes
2.20	Attributes of IBM x-series MCMs
2.21	Differences in POWER4 and POWER5 Chips
2.22	Comparison of MCM Substrate Technology
2.23	SiP for Computers and Communications (millions of units)
2.24	Automotive Electronics Operating Environment
2.25	Automotive SiP Projections (millions of units)
2.26	Military/Aerospace SiP Projections (thousands of units)
4.1	Japan's Environmentally Friendly Material Trends
6.1	Competency Matrix of SATS and EMS Providers
7.1	SiP Critical Requirements Forecast
7.2	System-in-a-Package Requirements
7.3	Selected Single Chip Package Potential Solutions