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3D Integration at the Wafer Level

Driven by the need for improved performance, a number of companies are researching methods to use short vertical interconnections to replace the long interconnects found in 2D structures. Stacking disparate technologies to provide a structure with potential functions including logic, memory, MEMS, antennas, display, RF, analog/digital, sensors, and power storage is potentially possible with 3D heterogeneous integration, making this technology the “Holy Grail” of system integration. The new 3D options include both wafer-to-wafer stacking and chip-to-wafer stacking. This analysis highlights the drivers for the technology and the activities of companies, research organizations, and universities.

Key in the development of the technology is the use of through wafer vias, wafer thinning, and the ability to bond these new structures. Through wafer via options include deep etch capability such as the anisotropic “Bosch etch.” Innovative solutions are being developed by a number of companies and include insulator formation by CVD TEOS or polymers. Conductor options include copper, tungsten, or poly silicon. Wafer thinning features lapping/grinding followed by wet etch, plasma etch, or CMP. Bonding options include silicon or metal fusion, Cu/Sn eutectic, polymer bonding, and bumping.

	3D Integration at the Wafer Level
File size: 84.1 kb		Published: March 2006

Table of Contents
	Executive Summary
	Introduction
1.	Delay in Implementing Low-k
1.	System-on-a-Chip
1.	System-in-Package
1.	Wafer Level 3D
1.4.	Key Enabling Technologies
1.4.	3D Technology Issues
1.4.	Enabling Unit Operations
	Unit Operations for 3D Integration
2.	Through Wafer Vias
2.1.	Deep Via Etching
2.1.	Laser Drilled Vias
2.1.	Deep Trench Capacitor Technology
2.	Via Fill
2.2.	CVD SiO2 Insulator
2.2.	Conformal Organic Insulators
2.2.2.	Parylene
2.2.2.1.	Parylene Stress and Physical Property Issues
2.2.2.1.	Reactivity of Organic Fluoride with Ta and Ti
2.2.2.	BCB
2.2.2.	Fill and Drill
2.	Diffusion Barrier/Adhesion Layer
2.	Metallization
2.4.	Plating
2.4.	MOCVD
2.4.	Vias Last Copper Plug Via Resistance
2.	Thinning
2.5.	Backgrinding
2.5.	Plasma Etching
2.5.	Wet Etching
2.5.	CMP
2.5.	Dicing
2.5.	Impact of Thinning on Electrical Characteristics
2.	Alignment and Bonding
2.6.	Wafer-to-Wafer Bonding
2.	Wafer Bonding Options
2.7.	Eutectic Bonding
2.7.	Polymer Adhesive Bonding
2.7.	Bump Bonding
2.7.3.	Indium
2.7.3.	Indium/Gold Bumps
2.7.3.	Gold Bumps
2.7.3.	Lead/Tin Solder Bumping
2.7.	Direct Fusion Bonding
2.7.4.	Silicon Fusion Bonding
2.7.4.	Direct Copper Bonding
2.7.4.	Wafer-to-Wafer and Die-to-Wafer Bonding
2.7.	Bonding Comparisons
2.	Processing on Topography
2.8.	Spray Coating
	Commercial 3D Integration Activities
3.	IBM
3.	Infineon
3.	Intel
3.	Micron Technology
3.	Oki Electric
3.	Philips
3.	Renesas Technology
3.	Samsung Electronics
3.	Tezzaron Semiconductor
3.1	Toshiba
3.1	Ziptronix
3.1	ZyCube
3.1	Research Consortia, Institutes, and Universities
3.13.	Association of Super Advanced Electronic Technologies
3.13.	Cornell
3.13.	Defense Advanced Research Projects Agency
3.13.	IMEC
3.13.	Fraunhofer-IZM Munich
3.13.	Lincoln Labs
3.13.	Massachusetts Institute of Technology
3.13.	Rensselaer Polytechinc Institute
3.13.	Research Triangle Institute
3.13.1	Sandia National Labs
3.13.1	International SEMATECH
3.13.1	Tohoku University
3.13.1	University of Arkansas
	Process Comparisons
4.	Wafer-to-Wafer and Chip-to-Wafer Assembly
4.	Via Size and Aspect Ratio
4.	Silicon Deep Via Etching
4.	Vias First versus Vias Last
4.	Via Insulation
4.	Via Barrier Layers and Metallization
4.	Handle Wafer Technology
4.	Wafer-to-Wafer and Die-to-Wafer Bonding Technologies
4.	CMOS Device Compatibility
4.1	Manufacturing Options
	Barriers to Commercialization
5.	Design
5.	Thermal Issues
5.	Test
	Infrastructure and Timing
	Market Trends
7.	History of 3D Packages
7.1.	Irvine Sensors
7.1.	Vertical Circuits
7.1.	3D Plus
7.	Drivers for Through Via Commercialization
7.	Applications for Through Silicon Vias
7.3.	Flash Memory
7.3.	DRAM and SRAM Stacks
7.3.	Image Sensors
7.3.	Processor and DRAM Stacks

List of Figures
1	Electronic systems integration.
2	3D integration through via adoption time line.
1.1.	Delay in low-k implementation.
1.2.	Relationship between delay and feature scaling.
1.3.	System-on-Chip.
1.4.	Global interconnect lengthsSOC versus 3D.
1.5.	3D stacking of disparate technologies.
1.6.	Wafer stacking.
2.1.	Bosch etch process.
2.2.	Sidewalls with Bosch process versus Unaxis process.
2.3.	Laser drilled silicon through vias.
2.4.	Normalized PECVD nitride thickness versus via aspect ratio.
2.5.	Parylene coating process.
2.6.	Copper migration in various dielectrics.
2.7.	MOCVD deposition of TiN from TDEAT.
2.8.	Options for copper plating.
2.9.	Effect of ethyl iodide addition on growth rate of MOCVD copper.
2.10.	Normalized break strength versus thinning technique.
2.11.	Coarse versus fine grinding.
2.12.	Sawing before and after thinning.
2.13.	Dicing by thinning process.
2.14.	EVG SmartView® wafer alignment process.
2.15..	Suss MicroTec align and bond cluster.
2.16.	Wafer bonding techniques.
2.17.	BCB bond strength versus thickness.
2.18.	Indium bumping.
2.19.	Plated gold bumps.
2.20.	Plated solder bump process flow.
2.21.	Solder bumps before and after reflow.
2.22.	Anneal conditions for TEOS-based SiO2 - SiO2 bonding.
2.23.	Bonded Cu/Cu interface.
3.1.	Proposed IBM process.
3.2.	Infineon's SOLID process flow.
3.3.	F2F SOLID contact.
3.4.	Intel 3D technology prototype design.
3.5.	Oki Electric roadmap for 3D memory modules.
3.6.	Renesas chip-to-chip interconnection technique.
3.7.	Renesas process for through hole formation.
3.8.	Renesas demonstration package.
3.9.	Samsung's wafer-level process.
3.10.	DDR memory repartitioning.
3.11.	Tezzaron fabrication process.
3.12.	ZyCube 3D technology.
3.13.	ASET process overview.
3.14.	ASET's copper through vias.
3.15.	SEM cross section of 20µm pitch through vias.
3.16.	Copper stud after passivation and CMP.
3.17.	IMEC copper nail.
3.18.	Vertical system integration with polymer bonding.
3.19.	Vertical system integration by Cu-Sn-Cu eutectic bonding.
3.20.	Chip-to-wafer handling.
3.21.	Lincoln Labs process.
3.22.	MIT process flow.
3.23.	RPI process.
3.24.	Wafer alignment accuracy.
3.25.	RTI's 3D process.
3.26.	3D interconnects with high aspect ratios.
3.27.	Sandia's IST technology.
3.28.	3D image sensor chip configuration.
3.29.	3D image sensor cross section.
3.30.	Vertical interconnect after plasma etch, oxidation, and via filling.
3.31.	SEM cross-section of 3D image sensor chip.
3.32.	Via developed using TSV process.
4.1.	Options for 3D integration.
5.1.	Area left in a cell for post fab via formation.
5.2.	Thermal resistance measurement results.
7.1.	ZyCube product roadmap.
7.2.	VCI DRAM stack.
7.3.	3D Plus SRAM stack.
7.4.	3D integration through via adoption time line.
7.5.	3D reconfigurable image processor.
7.6.	Image sensor.
7.7.	CCD package structure.
7.8.	Stacked memory and processors.
7.9.	3D computer chip.
7.10.	3D communication processor.
7.11.	ASET system processor.

List of Tables
2.1.	Properties of Parylene
2.2.	Roughness of Typical SiO2 Surfaces
3.1.	Current and Projected Via Properties
3.2.	Copper Plating Additives
4.1.	3D Process Configurations
4.2.	Via Etching Methods
4.3.	Insulator and Metallization Selections
4.4.	Bonding Choices
7.1.	Stacking Method Comparison