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ADVANCED PACKAGING UPDATE:
Market and Technology Trends
Vol. 3-010

This issue of the Advanced Packaging Update provides the economic outlook and examines the general macroeconomic trends in the world economy and the microeconomic trends in the semiconductor packaging and assembly industry. IC package subcontractor revenues for 2010 are examined and plans for CAPEX spending in 2011 are compared with actual 2010 and 2009 expenditures. The report features an update of copper wire bond developments and in-depth reviews of bonding capillaries designed for copper wire and special molding compound formulations. The latest developments in 3D through silicon via (TSV) are analyzed and the issues companies face in moving the technology into volume production are discussed.

	Advanced Packaging Update: Market and Technology Trends Vol. 3-010
File size: 397kb		Published: February 2011.

Table of Contents
1	Industry and Economic Trends
1.1	Economic Trends
1.1.1	Macroeconomic Trends
1.1.2	Recovery in the Electronics Industry
1.2	Foundry Shipments and CAPEX Increase
1.3	Semiconductor Packaging and Assembly
2	Copper Wire Bond
2.1	Material Improvements
2.1.1	Hitachi Chemical Co., Ltd.
2.1.2	Sumitomo Bakelite Co., Ltd.
2.2	Capillaries for Copper Wire Bonding
2.2.1	Adamant Kogyo Co., Ltd
2.2.2	Gaiser Precision Bonding Tools
2.2.3	K&S
2.2.4	Small Precision Tools (SPT)
2.2.5	STATS ChipPAC
2.2.6	TOTO Advanced Ceramics
2.3	Copper Wire Bonding Process
3	3D TSV Status and Developments
3.1	3D TSV Applications and Drivers
3.1.1	Memory
3.2	Issues for TSV Production and Progress
3.2.1	Design
3.2.2	Process Development
3.2.3	Assembly and Test
3.2.4	Reliability Data
3.3	Silicon Interposers with TSVs
3.3.1	Xilinx
3.3.2	Semtech and IBM
3.3.3	Intelligent Chip Connections Pte, Ltd.
	References

List of Figures
1.1.	Monthly U.S. housing starts.
2.1.	Number of K&S copper kits installed (2005 – 2010).
2.2.	Factors affecting copper wire reliability in HAST.
2.3.	Biased/unbiased HAST and PCT for different mold compounds.
2.4.	Wire bonding capillary.
2.5.	Light matte finish on Adamant capillary, compared to competitor.
2.6.	Wear and debris on Adamant capillary after two million bonds.
2.7.	CuPRAplus™ capillary to reduce wire slippage.
2.8.	Process window for CuPRAplus™ capillary.
2.9.	Granular surface of the CuPRA3G™ capillary.
2.10.	CuPRA3G™ lifetime for a 33µm bare copper wire.
2.11.	Copper wire bonds with standard capillary vs. SPT's SU capillary.
2.12.	Pull test results with SU capillary compared to other finishes.
2.13.	Reduced defects with SU capillary compared to other finishes.
2.14.	Design features of TOTO's copper wire bonding capillary.
2.15.	TOTO's matte tip surface for copper wire.
2.16.	K&S ProCu first bond process.
2.17.	Second bond window with bare and PCC wire.
2.18.	Bonding process window with bare and PCC wire.
3.1.	Wide I/O package solutions.
3.2.	Micron's stacked memory structure.
3.3.	Proposed standards for 3D design flow.
3.4.	Non-contact scanning concept.
3.5.	Xilinx silicon interposer structure.
3.6.	IBM's silicon interposer.
3.7.	ICC's process flow.

List of Tables
1.1.	Semiconductor Packaging Materials Market
1.2.	IC Package Subcontractor Revenue
1.3.	Subcontractor CAPEX Growth (millions of dollars)
3.1.	3D TSV Applications: Status, Drivers, and Barriers