| List of Figures |
| 1.1. |
Housing starts 2006-2008. |
| 2.1. |
Gold price trends. |
| 2.2. |
Copper price trends. |
| 2.3. |
QFP and PBGA assembly price trends and projections. |
| 2.4. |
QFN and laminate CSP assembly price trends and projections. |
| 3.1. |
Total worldwide market for copper bonding wire. |
| 3.2. |
Aluminum splash on die pad after copper wire bonding. |
| 3.3. |
EFO set-up for (a) gold and (b) copper wire bonding. |
| 3.4. |
Wire material cost saving for copper vs. gold. |
| 3.5. |
Bond pad splash due to copper wire bonding force. |
| 3.6. |
X-ray images of gold (left) and copper wires (right). |
| 3.7. |
Cross-section of copper wire bond on 65nm low-k device. |
| 3.8. |
K&S's four types of copper bonding wire. |
| 3.9. |
Copper wire bonded part from Unisem. |
| 3.10. |
Total packaging cost for gold vs. copper wire part. |
| List of Tables |
| 2.1. |
Average QFP Assembly Price Trends (1 million/month) |
| 2.2. |
QFP Assembly Prices in 2008 |
| 2.3. |
Average Wire Bond PBGA Assembly Price Trends |
| 2.4. |
Average Wire bond PBGA Assembly Prices in 2008 |
| 2.5. |
Average Flip Chip PBGA Assembly Prices (including substrate) |
| 2.6. |
Average Laminate CSP Assembly Prices |
| 2.7. |
Average Wire Bond QFN Assembly Price Trends |
| 2.8. |
QFN Assembly Prices in 2008 |
| 3.1. |
Evaluation of Copper as a Replacement for Gold Bonding Wire |
| 3.2. |
Cost Savings of Using Copper Wire Bonding |
| 3.3. |
Material Properties of Gold, Aluminum, Copper, and MaxSoft |
| 3.4. |
Cost Savings of Copper and Palladium-coated Copper Wire |
| 3.5. |
SPIL Roadmap for Fine Copper Wire Bonding |
| 3.6. |
Material Challenges for Copper Wire and Solutions |
| 3.7. |
Cost Reduction Due to Copper Wires at STMicroelectronics |
| 4.1. |
Selected Build-up Flip Chip Substrate Suppliers |
| 4.2. |
Selected Laminate PBGA/CSP Substrate Suppliers |
| 4.3. |
Design Rules for ASE PBGA/CSP Substrates |
| 4.4. |
Design Rules for Daisho Denshi PBGA/CSP Substrates |
| 4.5. |
Design Rules for Eastern PBGA/CSP Substrates |
| 4.6. |
Design Rules for Endicott Interconnect CoreEZ® Substrates |
| 4.7. |
Design Rules for Endicott Interconnect HyperBGA® Substrate |
| 4.8. |
Design Rules for FICT's Flip Chip Substrates |
| 4.9. |
Design Rules for JCI CSP Substrates |
| 4.10. |
Design Rules for Kinsus Flip Chip Substrates |
| 4.11. |
Design Rules for Kinsus PBGA/CSP Substrates |
| 4.12. |
Design Rules for Kyocera Flip Chip Substrates |
| 4.13. |
Design Rules for Microcircuit PBGA/CSP Substrates |
| 4.14. |
Design Rules for Mitsui Chemicals PBGA/CSP Substrates |
| 4.15. |
Design Rules for Nan Ya PCB Flip Chip Substrates |
| 4.16. |
Design Rules for Nan Ya PCB PBGA Substrates |
| 4.17. |
Design Rules for TNCSi Flip Chip Substrates |
| 4.18. |
Design Rules for NTK Flip Chip Substrates |
| 4.19. |
Design Rules for PPT Flip Chip Substrates |
| 4.20. |
Design Rules for PPT PBGA/CSP Substrates |
| 4.21. |
Design Rules for Samsung's PBGA/CSP Substrates |
| 4.22. |
Design Rules for Samsung Techwin's BOC Substrates |
| 4.23. |
Design Rules for Shinko Flip Chip Substrates |
| 4.24. |
Design Rules for Shinko PBGA/CSP Substrates |
| 4.25. |
Design Rules for Simmtech PBGA/CSP Substrates |
| 4.26. |
Design Rules for CSP Substrates |
| 4.27. |
Design Rules for Tripod's PBGA/CSP Substrates |
| 4.28. |
Design Rules for Unimicron Flip Chip Substrates |
| 4.29. |
Design Rules for Unimicron PBGA/CSP Substrates |
