TechSearch
International, Inc.
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4801 Spicewood
Springs Rd.,
Suite #150,
Austin, TX 78759
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Tel: 512.372.8887
Fax: 512.372.8889
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 BGA/CSP DEVELOPMENT UPDATE SERVICE
First Quarter, 2004
The first quarterly BGA/CSP update for 2004 highlights developments and trends in stacked die CSPs and stacked packages. Also featured is a discussion of the latest applications using stacked die packages. Issues related to die stacking are discussed, including wafer thinning, bare die, known good die, die attach and wire bond, and thermal dissipation. A new substrate technology for memory modules from ThermalWorks is discussed. The report also includes a section on a new automated semiconductor package burn-in and test solution introduced by Unisys. Mindspeed’s new low-cost technique for biased humidity stress testing is also described. solder balls are provided.
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Q1, 2004: BGA/CSP Development Update Service |
| File size: 56.8 kb |
Published: May 2004. |
| Table of Contents |
| 1 |
Stacked Die Packages |
| 1.1 |
Challenges for Stacked Die Packages |
| 1.1.1 |
Bare Die and KGD |
| 1.1.2 |
Wafer Thinning |
| 1.1.3 |
Die Attach and Wire Bonding |
| 1.1.4 |
Thermal Dissipation |
| 1.2 |
Company Overview |
| 1.2.1 |
Amkor Technology |
| 1.2.2 |
ASE |
| 1.2.3 |
ChipPAC |
| 1.2.4 |
Fujitsu |
| 1.2.5 |
Intel |
| 1.2.6 |
NEC |
| 1.2.7 |
Sandisk |
| 1.2.8 |
Sharp |
| 1.2.9 |
SPIL |
| 1.2.10 |
Texas Instruments |
| 1.2.11 |
Toshiba |
| 1.2.12 |
UTAC |
| 2 |
Stacked Packages |
| 2.1 |
Irvine Sensors |
| 2.2 |
Staktek |
| 2.3 |
3-D Plus |
| 2.4 |
Vertical Circuits |
| 3 |
New Memory Module Substrate |
| 4 |
New Developments in Test |
| 4.1 |
Unisys Automated Burn-in and Test System |
| 4.2 |
Mindspeed’s New Low-Cost HAST |
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| List of Figures |
| 1.1. |
Amkor’s roadmap for stacked die package height. |
| 1.2. |
Trend in number of stacked die at Amkor. |
| 1.3. |
Trend in stacked products at Amkor. |
| 1.4. |
Amkor’s stacked etCSP. |
| 1.5. |
Stacked product roadmaps for ASE. |
| 1.6. |
Package-in-Package structure. |
| 1.7. |
palmOne’s Tungsten™ T3. |
| 1.8. |
Intel’s Folded Stacked CSP (FSCSP). |
| 1.9. |
Sharp’s packaging roadmap. |
| 1.10. |
SPIL’s stacked die package roadmap. |
| 1.11. |
Toshiba’s stacked die packages. |
| 1.12. |
UTAC’s stacked die package roadmap. |
| 2.1. |
Area of TSOP diced to form stacked package. |
| 2.2. |
Stacked package configurations. |
| 2.3. |
Staktek’s high performance memory module. |
| 2.4. |
3-D Plus process flow. |
| 3.1. |
Stablcor® PCB thermal performance |
| 3.2. |
Cross-section of module with Stablcor®. |
| 4.1. |
Unisys ATS500 Automated Test System |
| List of Tables |
| 1.1. |
Stacked Die and Stacked Package Tradeoffs |
| 1.2. |
Minimum Package Thickness |
| 1.3. |
Amkor’s Stacking Trends by Device Type |
| 1.4. |
Amkor’s Stacking Trends by Number of Die |
| 1.5. |
ASE’s Die Stacking Trends by Device Type |
| 1.6. |
ASE’s Die Stacking Trends by Number of Die |
| 1.7. |
ASE’s Core Technologies for Stacked Die |
| 1.8. |
Stacked Products at ASE |
| 1.9. |
ChipPAC’s Stacked Die Trends by Device Type |
| 1.10. |
ChipPAC’s Stacked Die Trends by Number of Die |
| 1.11. |
Stacked Products at ChipPAC |
| 1.12. |
ChipPAC’s Stacked Package Trends by Device |
| 1.13. |
ChipPAC’s Stacked Package Trends by Die |
| 1.14. |
Fujitsu’s Stacked Die Trends by Device Type |
| 1.15. |
Fujitsu’s Stacked Die Trends by Number of Die |
| 3.1. |
Selected Material Properties for Stablcor® |
| 4.1. |
Temperature, Relative Humidity, and Duration |
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