TechSearch
International, Inc.
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4801 Spicewood
Springs Rd.,
Suite #150,
Austin, TX 78759
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Tel: 512.372.8887
Fax: 512.372.8889
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 BGA/CSP DEVELOPMENT UPDATE SERVICE
Third Quarter, 2003
The third quarterly BGA/CSP update for 2003 features special coverage of assembly issues for silicon devices with low-k dielectrics, including bonding over active I/Os and flip chip. Highlighted are activities at major companies. The report also includes a section on packaging trends for mobile phones, including package types, pitch trends, and motherboard technology. Featured are new 0.4mm pitch CSPs. A special section on packaging trends for DRAM memory products described the shift from TSOPs to FBGAs. The section also contains developments in wafer level packages, featuring the new wafer level packages from TwinMOS and Infineon. The report also includes a discussion on HAST for laminate substrates and when the test is appropriate.
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Q3, 2003: BGA/CSP Development Update Service |
| File size: 30.6 kb |
Published: October 2003. |
| Table of Contents |
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1 |
Assembly Issues for Silicon with Low-k Dielectrics |
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1.1 |
Wire Bonding over Active Circuitry |
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1.2 |
Assembling Components with Low-k Dielectric |
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1.3 |
Altera |
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1.4 |
Amkor Technology |
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1.5 |
ASE |
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1.6 |
IBM Microelectronics |
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1.7 |
K&S |
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1.8 |
LSI Logic |
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1.9 |
Motorola |
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1.10 |
TSMC |
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2 |
Mobile Phone Packaging Trends |
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2.1 |
Package and Board Trends |
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2.2 |
CSP Pin Count and Pitch Trends |
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2.3 |
Reliability Data for 0.4mm Pitch CSPs |
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3 |
DRAM Packaging Trends |
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3.1 |
Drivers for CSPs |
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3.2 |
New DRAM Packages |
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3.2.1 |
Samsung |
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3.2.2 |
Micron Technology |
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3.2.3 |
TwinMOS and GEIL |
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3.2.4 |
Infineon |
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4 |
HAST and Reliability Testing: An Opinion |
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4.1 |
History and Definitions |
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4.2 |
Laminate Carriers and PCB Tests |
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4.3 |
Additional Documentation |
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4.3.1 |
Characteristics of Water |
| 4.3.2 |
Mechanisms of Vapor Entry |
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| List of Figures |
| 1.1. |
Example of wire bond pad peeling over low-k dielectric. |
| 1.2. |
Cross-section of a wire bond over active circuitry. |
| 2.1. |
Mova P504i and P504iS mobile phones. |
| 3.1. |
DRAM package trends. |
| 3.2. |
Technology consolidation roadmap. |
| 3.3. |
TwinMOS wafer level CSP. |
| 3.4. |
TwinMOS wafer level CSP transmission bandwidth. |
| 3.5. |
Infineon’s ELASTec™ bump with RDL. |
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4.1
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Saturation vapor pressure dependency on temperature.
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| List of Tables |
| 1.1. |
Selected Users and Suppliers of Wire Bond Pad on I/O |
| 1.2. |
Selected Low-k Dielectric Materials |
| 1.3. |
Selected Users and Suppliers of Devices with Low-k Dielectric |
| 2.1. |
Mobile Phone Package and Board Technology by Model |
| 2.2. |
Package Trends for Mobile Phones |
| 3.1. |
DDR2 Memory Package Examples |
| 4.1 |
Mechanisms of Vapor Entry |
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