TechSearch
International, Inc.
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4801 Spicewood
Springs Rd.,
Suite #150,
Austin, TX 78759
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Tel: 512.372.8887
Fax: 512.372.8889
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 BGA/CSP DEVELOPMENT UPDATE SERVICE
First Quarter, 2001
The first quarterly BGA/CSP update for 2001 features special coverage of the System-on-a-Chip (SoC) versus System-in-Package (SiP) debate, highlighting many SiPs available in BGA or CSP format. A discussion on new BGA packages, including tape, laminate, and ceramic packages, as well as packages for optoelectronic applications are provided. An update on the wafer level package market is provided along with new package introductions and developments. Highlighted are the K&S Flip Chip Division (formerly FCT) Polymer CollarTM Ultra CSPTM, Hitachi’s WPP2, and a list of wafer level packages in production.
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Q1, 2001: BGA/CSP Development Update Service |
| File size: 29.1 kb |
Published: April 2001. |
| Table of Contents |
| 1 |
SiP versus SoC |
| 1.1 |
Today’s SiPs |
| 1.1.1 |
ASE |
| 1.1.2 |
Alpine Microsystem’s Silicon Based HDI |
| 1.1.3 |
Amkor’s SiP Solutions |
| 1.1.4 |
ChipPAC’s Stacked CSPs |
| 1.1.5 |
Dense-Pac Microsystems’ Heterogeneous Stack |
| 1.1.6 |
Fujitsu Media Devices |
| 1.1.7 |
SyChip Silicon-on-Silicon Module |
| 1.1.8 |
Vertical Circuits, Inc. |
| 1.1.9 |
3D Plus |
| 2 |
Wafer Level Package Developments |
| 2.1 |
Market Trends for Wafer Level Packages |
| 2.2 |
New Wafer Level Package Developments |
| 2.2.1 |
Hitachi’s WPP2 |
| 2.2.2 |
K&S Flip Chip Division’s Polymer CollarTM WLP |
| 3 |
New Package Developments |
| 3.1 |
Kyocera’s BGA Package for Optoelectronics |
| 3.2 |
New Products Ship in BGAs |
| 3.2.1 |
Fujitsu’s BGAs |
| 3.2.2 |
Motorola’s PBGAs and TBGAs |
| 3.2.3 |
LSI Logic’s New Flip Chip Package Family |
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| List of Figures |
| 1.1 |
Intel’s IA-64 microprocessor |
| 1.2 |
Comparison of SiP and SoC for different silicon technologies |
| 1.3 |
Production schedule for Japanese SiPs, by construction category |
| 1.4 |
Rohm’s "Real Socket" SiP |
| 1.5 |
Alpine Miocrosystems’ SB HDI module for laptop CPU |
| 1.6 |
Graphical cross-section of SB HDI module |
| 1.7 |
Amkor’s stacked CSP |
| 1.8 |
Amkor’s stacked MCM |
| 1.9 |
Amkor’s stacked SiP |
| 1.10 |
ASIC + flash stack from ChipPAC |
| 1.11 |
Same die wire bonding |
| 1.12 |
ChipPAC CSP/SiP development |
| 1.13 |
Dense-Pac’s heterogeneous stack of prepackaged die |
| 1.14 |
Fujitsu Media Devices SiP module |
| 1.15 |
SyChip’s GPS receiver module |
| 1.16 |
VCI’s 1Gb SDRAM module with four die stacked |
| 1.17 |
3D Plus memory module |
| 2.1 |
High and low scenario WLP growth projections |
| 2.2 |
Hitachi’s WPP2 cross section |
| 2.3 |
Polymer CollarTM Ultra CSPTM |
| 3.1 |
Top and bottom of Kyocera America’s BGA OE package |
| 3.2 |
Process flow of current vs. automated assembly of OE package |
| List of Tables |
| 1.1 |
Comparison of SiP and SoC |
| 1.2 |
SiP Products Currently Available |
| 1.3 |
Electrical Performance of Alpine Microsystems’ SB HDI |
| 2.1 |
Wafer Level Packages in Production |
| 3.1 |
GigaModule Reliability Test Samples |
| 3.2 |
LSI Logic flx I/OTM Flip Chip Package Family |
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